The present invention relates generally to a programmable logic device including a plurality of programmable logic elements and capable of arbitrarily connecting those programmable logic elements and, more particularly, to a semiconductor integrated circuit capable of enhancing a using efficiency of combinational logical units and flip-flops which are included in the programmable logic elements.
For example, a PLD (Programmable Logic Device) and a FPGA (Field Programmable Gate Array) have hitherto been known as programmable logic devices constructed so that an arbitrary logical circuit can be actualized by the user's writing logic as a kind of data in the form of program data.
For instance, the conventional FPGA is composed mainly of: small-sized logical blocks (Programmable Logic Elements; PLEs) capable of programing logical functions; and wire elements capable of programmably connecting the small-sized logical blocks. FIG. 17 is a block diagram showing one example of, e.g., a field programmable gate array.
As illustrated therein, the field programmable gate array includes a plurality of small-sized programmable logical blocks (hereinafter referred to as [logical blocks]) 10 and programmable wire means provided lengthwise and crosswise between these logical blocks 10. The wire means have switch stations 20 capable of programmably connecting the logical blocks 10, I/O lines 22 extending from the switch stations 20 to the respective logical blocks 10 and inter switch station wires 24. Inputs and outputs of the respective logical blocks 10 are arbitrarily connectable through the wire means, i.e., the I/O lines 22, the switch stations (SS) 20 and the inter SS wires 24.
As described above, the small-sized logical blocks capable of programming the logical functions include a small number of I/O terminals. The user performs an operation to allocate the want-to-write circuits to the small-sized logical blocks just when writing to the field programmable gate array.
If such allocations are executed, the circuit designed by the user is divided into a plurality of small-sized logical blocks for attaining the circuit function thereof. Reversely speaking, the plurality of small-sized logical blocks are connected through the programmably connectable wire elements, thereby achieving one circuit function.
For example, when the user circuit contains multi-input multiplexers, the number of small-sized logical blocks to be divided increases in a case where the multiplexers are constructed of (1) the small-sized logical gates (e.g., combinational logical circuits) allocated to the small-sized logical blocks and (2) the programmable wires. A large proportion of the programmable portions (small-sized logical gates and wires) in the programmable logic device are consumed, resulting in such a problem that the gate using efficiency decreases.